Since the 386SL processor was introduced by the Intel Corporation, system management mode (SMM) has been available on IA32 processors as an execution mode that executes code loaded by BIOS or firmware. SMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEM-designed code.
Special-purpose operation modes are typically entered in response to an interrupt signal. For example in IA32 processors, SMM is entered in response to a System Management Interrupt (SMI) signal, while in some server processors a similar interrupt signal is referred to a processor management interrupt (PMI) signal. For simplicity, SMI and PMI signals are often referred to as xMI signals.
To date, most BIOS implementations that leverage the SMM capability of the foregoing Intel processors simply register a monolithic section of code that is created during the build of the BIOS to support a specific function or set of functions particular to systems that use the BIOS. Furthermore, in multi-processor systems, in response to an xMI signal, all processors are activated into a management mode. However, only one processor services the xMI request, while the rest of the processors wait to re-enter normal operation. Therefore, as the number of cores on a single processor grow from two and four cores to larger numbers, such as sixteen and thirty two cores, a potentially greater number of processor are idle during a management mode.
In addition to the number of cores growing on processors, the amount of memory available in a platform is also expanding at a rapid rate. As a result, functions such as memory migration, i.e. the moving of data/information from one portion of memory to another portion of memory, require more execution time and power to complete. Consequently, the longer execution times of tasks, such as memory migration, in combination with the growing number of cores, results in a larger amount of time that greater processing resources sit idle wasting potential execution power.